The invention relates generally to video decoding systems and methods and more particularly to video decoding apparatus methods for systems that split decoding between at least two processing units and use commands to synchronize between those units.
Video decoders, such as MPEG video decoders and other decoders, decode incoming compressed streams of video. Depending upon the type of video encoding, a video decoder may have associated with it a forward reference buffer, a backward reference buffer, a decoding buffer and a display buffer. A display engine displays data that is stored in the frame buffer so separate buffers are used for storing partially decoded data and filly decoded data in different buffers. For high resolution TV formats (HDTV 1920xc3x971080) the required buffers may, amount to approximately 12 megabytes (4xc3x971920xc3x971080xc3x971.5 bytes). Using four different buffers can result in the unnecessary use of large amounts of costly memory.
For example, video decoders are known which include a software module typically executed by a host processor, that provides a sequence of commands to a hardware part of video decoder that includes a command to have a video decoder wait for an event to occur, such as the end of a frame scan to occur so that writing can commence to a particular buffer. The command stream, as known in the art, provides commands to a video decoding process which may decode video using a hardware decoder that may provide variable length decoding, inverse quantization, inverse discrete cosine transform (IDCT), motion compensation, or other suitable decoding operations. A command FIFO in front of the video decoder receives the command stream from the host processor. The decoding process in the video decoder typically uses four buffers. A forward reference buffer, a backward reference buffer, a decoding buffer, which may contain partially decoded information, and a display buffer which contains finally decoded video for display such as for overlay displays or other displays. For example, decoding commands in a command FIFO may be stalled until an entire frame has been displayed. For example, when the display engine has read and displayed the end of a frame or field from the display buffer. However, the use of the four buffers results in large amounts of costly memory in a graphics controller chip or other integrated circuits.
To reduce the amount of required memory, other conventional video decoders may share frame buffer addresses on a macro block, or row of macro blocks basis. For example, a hardware decoder may share the decoding buffer and display buffer to reduce memory size. In such systems, the hardware decoder receives data over a host bus, whereafter the hardware decoder provides a stall signal to a decoding block. This stall signal is based on the comparison of the current address that contains fully decoded information for display during this frame scan with the storage address for new data that will be displayed during a later frame scan, so that the hardware decoder can delay decoding information into the same buffer. Such systems can require large integrated circuitry which results in higher fabrication costs and lower process yields. Such decoders effectively generate their own commands and operating signals to determine buffer locations, and typically do not receive stall commands from a host processor. Such systems that share a frame buffer for both decoding and displaying, use three buffers instead of four buffers, but the larger amounts of hardware required can additionally increase the cost of the video processing portion.
Accordingly, there exists a need for an improved video decoding apparatus and method that uses a shared frame buffer memory for both decoding and displaying.